Here are the texts from the Datasheet for the ENC28J60 describing the power saving feature.
The ENC28J60 may be commanded to power-down via the SPI interface. When powered down, it will no longer be able to transmit and receive any packets.
To maximize power savings:
1. Turn off packet reception by clearing ECON1.RXEN.
2. Wait for any in-progress packets to finish being received by polling ESTAT.RXBUSY. This bit should be clear before proceeding.
3. Wait for any current transmissions to end by
confirming ECON1.TXRTS is clear.
4. Set ECON2.VRPS (if not already set).
5. Enter Sleep by setting ECON2.PWRSV. All MAC, MII and PHY registers become inaccessible as a result. Setting PWRSV also
clears ESTAT.CLKRDY automatically.
In Sleep mode, all registers and buffer memory will maintain their states. The ETH registers and buffer memory will still be accessible by the host controller.
Additionally, the clock driver will continue to operate.
The CLKOUT function will be unaffected (see Section “CLKOUT Pin”).
When normal operation is desired, the host controller must perform a slightly modified procedure:
1. Wake-up by clearing ECON2.PWRSV.
2. Wait at least 300 μs for the PHY to stabilize. To accomplish the delay, the host controller may poll ESTAT.CLKRDY and wait for it to become set.
3. Restore receive capability by setting
After leaving Sleep mode, there is a delay of many milliseconds before a new link is established (assuming an appropriate link partner is present). The host controller may wish to wait until the link is established
before attempting to transmit any packets. The link status can be determined by polling the PHSTAT2.LSTAT bit. Alternatively, the link change interrupt may be used if it is enabled. See Section “Link Change Interrupt Flag (LINKIF)” for additional details.
The CLKOUT has an internal prescaler which can divide the output by 1, 2, 3, 4 or 8. The CLKOUT function is enabled and the prescaler is selected via the ECOCON register.
To create a clean clock signal, the CLKOUT pin is held low for a period when power is first applied. After the Power-on Reset ends, the OST will begin counting.
When the OST expires, the CLKOUT pin will begin outputting its default frequency of 6.25 MHz (main clock divided by 4). At any future time that the ENC28J60 is reset by software or the RESET pin, the CLKOUT function
will not be altered (ECOCON will not change value). Additionally, Power-Down mode may be entered and the CLKOUT function will continue to operate. When Power-Down mode is cancelled, the
OST will be reset but the CLKOUT function will continue. When the CLKOUT function is disabled (ECOCON = 0), the CLKOUT pin is driven low.
Link Change Interrupt Flag (LINKIF)
The LINKIF indicates that the link status has changed.
The actual current link status can be obtained from the PHSTAT1.LLSTAT or PHSTAT2.LSTAT. Unlike other interrupt sources, the link status change interrupt is created in the integrated PHY module; additional steps must be taken to enable it.
By Reset default, LINKIF is never set for any reason. To receive it, the host controller must set the PHIE.PLNKIE and PGEIE bits. After setting the two PHY interrupt enable bits, the LINKIF bit will then shadow the contents of the PHIR.PGIF bit. The PHY only supports one interrupt, so the PGIF bit will always be the same as the PHIR.PLNKIF bit (when both PHY
enable bits are set).
Once LINKIF is set, it can only be cleared by the host controller or by a Reset. If the link change interrupt is enabled (EIE.LINKIE = 1, EIE.INTIE = 1, PHIE.PLNKIE = 1 and PHIE.PGEIE = 1), an interrupt will be generated by driving the INT pin low. If the link change interrupt is not enabled (EIE.LINKIE = 0, EIE.INTIE = 0, PHIE.PLNKIE = 0 or PHIE.PGEIE = 0), the host controller may poll the ENC28J60 for the PHIR.PLNKIF bit and take appropriate action. The LINKIF bit is read-only. Because reading from PHY registers requires non-negligible time, the host controller may instead set PHIE.PLNKIE and PHIE.PGEIE and then poll the EIR.LINKIF bit. Performing an MII read on the PHIR register will clear the LINKIF, PGIF and PLNKIF bits automatically and allow for future link status
I hope it will help to you.
mikroElektronika [Support team]